| Phone 470-883-9593 Email esarkar6@gatech.edu Linkedin linkedin.com/in/eknath-sarkar |
Research Interests
His current research focuses on low-temperature logic technologies using Si FinFET and Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits.
Doctoral Student
Bio
Eknath Sarkar earned his undergraduate degree in Physics from the University of Calcutta in 2016 and completed his Master’s in Electronics from Jadavpur University in 2018, where he was the Valedictorian and received a Gold medal. He worked as a Thin-film development engineer at Young Optics Inc, in Taiwan for three years. In 2023, he joined Georgia Tech’s STaR lab.
Selected Publications
1. Eknath Sarkar, Yu-Rui Chen, Jih-Chao Chiu, Zefu Zhao, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan and C. W. Liu, “Memory Window Enlargement by ZnO Incorporation in Top-Gated Self-Aligned a-InGaZnO FeFETs with High Endurance >1E11 Cycles” 3rd Symposium on Nano-Device Circuits and Technologies (SNDCT), Hsinchu, Taiwan, May 18-19, 2023.
2. Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, and C. W. Liu, “First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61 mV/dec, Ioff<10-7mA/mm, DIBL=44 mV/V, Positive VT, and Process Temp. of 300 oC,” accepted by Symposium on VLSI Technology and Circuits (VLSI), JUNE 11- 16, 2023.
3. Eknath Sarkar, Yichen Ma, Yu-Chieh Lee and C. W. Liu, “”Effects of Deep Trench Isolation Shape and Microlens Radius of Curvature on Optical and Electrical crosstalk in Backside Illuminated CMOS Image Sensors,” 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), Hsinchu, Taiwan, 2023, pp. 1-2, doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134452. (Best Student Poster award).